How do you manage to draw this out for over 20 minutes? He even gets some of the basics like Zen 4 FCLK/UCLK sync wrong.
It's this simple:
UCLK is the clock frequency of the memory controller
MCLK is the clock frequency of the memory
FCLK is the clock frequency of the infinity fabric interconnect.
On Zen 1, these clock frequencies are always in sync.
On Zen 2 and Zen 3, running UCLK and FCLK at the same frequency reduces memory latency by a significant number of clock cycles. The goal is generally to run at the highest possible UCLK and FCLK (whichever caps out lower is the limit).
On Zen 4, running UCLK and FCLK at the same frequency provides no memory latency reduction. The goal here is to run at the highest possible MCLK and FCLK. UCLK = MCLK/2 is a very small performance deficit, so the tradeoff makes sense even if you only gain 10% MCLK.