this post was submitted on 22 Nov 2023
1 points (66.7% liked)
AMD
25 readers
1 users here now
For all things AMD; come talk about Ryzen, Radeon, Threadripper, EPYC, rumors, reviews, news and more.
founded 11 months ago
MODERATORS
you are viewing a single comment's thread
view the rest of the comments
view the rest of the comments
How do you manage to draw this out for over 20 minutes? He even gets some of the basics like Zen 4 FCLK/UCLK sync wrong.
It's this simple:
UCLK is the clock frequency of the memory controller
MCLK is the clock frequency of the memory
FCLK is the clock frequency of the infinity fabric interconnect.
On Zen 1, these clock frequencies are always in sync.
On Zen 2 and Zen 3, running UCLK and FCLK at the same frequency reduces memory latency by a significant number of clock cycles. The goal is generally to run at the highest possible UCLK and FCLK (whichever caps out lower is the limit).
On Zen 4, running UCLK and FCLK at the same frequency provides no memory latency reduction. The goal here is to run at the highest possible MCLK and FCLK. UCLK = MCLK/2 is a very small performance deficit, so the tradeoff makes sense even if you only gain 10% MCLK.
This is incorrect, it's a very substantial latency step reduction and offers ideal performance in certain workloads. 8000/2000/2000 tests lower latency than 8000/2000/2200 and around 4ns lower than 8000/2000/2033.
There's even a flag in ryzen master which shows if uclk=fclk sync mode is active or not.