Intel

FWIW, if this is a fake, someone put an enormous amount of work into irrelevant things e.g. mechanical dimensions.

Eg: they have an 8MB L4 cache on the CPU die for LNL when MTL has a 128MB cache on SOC die.

The 8 MB is not an L4 cache since it is in parallel with the last level cache rather than above it in the hierarchy. This detail actually looks credible since it is a logical progression from MTL where the GPU memory access was also split off from the LLC. Now they're splitting off the rest.

Probably limited capacity and priorities

when MTL has a 128MB cache on SOC die.

It doesn't tho

And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.

Idk, it looks very similar to this

And why use N3 when Intel will have Backside power with their 3nm node?

Bcuz they are lame lol.

Intel talked about using TSMC N3 nodes in their products before. It won't be too surprising to see it in client CPU tiles as well.