this post was submitted on 20 Nov 2023
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Intel

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[–] [email protected] 1 points 11 months ago

FWIW, if this is a fake, someone put an enormous amount of work into irrelevant things e.g. mechanical dimensions.

Eg: they have an 8MB L4 cache on the CPU die for LNL when MTL has a 128MB cache on SOC die.

The 8 MB is not an L4 cache since it is in parallel with the last level cache rather than above it in the hierarchy. This detail actually looks credible since it is a logical progression from MTL where the GPU memory access was also split off from the LLC. Now they're splitting off the rest.