Hardware

The die space is only one part of the puzzle. The other - AMD's achilles heel no less - is software support. I mean, Phoenix has XDNA already, but from everything I've read, it's a PITA to actually use and rather limited by its currently available driver API, and as a consequence, barely any ML library/framework support as of now.

Just like they refuse to support consumer cards officially

This. AMD struggles with making drivers that don't crash or get you VAC banned. They're going to have to clear that bar before they can really start competing

Nah, throughput of tensor cores is far to high to compete against

Keep in mind too if they haven't already made these decisions to inovate and invest 4+ years ago, then any solution they come up with is still years away. Chip development is a 5+ year cycle from concept to implementation.

You seem to know more than me so forgive is this is out of place, but how are they incapable of getting performance out of their GPUs?

I mean they basically have an answer for everything except nvidias absolute top of the line, and their RT is one generation behind. Don’t they have slightly better raster performance too at similar price points?

Excuse me if you were just being hyperbolic but the notion that AMD cant answer one card from NVIDIA and thus they are complete shit is a bit hyperbolic to me

I am pretty sure they already have something in the pipeline, its just that it can take half a decade from low level concept to customer sales...

I hope they eventually implement a proper dedicated unit like Nvidia and Intel have.

That's what RDNA4 will introduce.

There's not really anything intrinsically /wrong/ with tying it to the same latency-hiding mechanisms as the texture unit (there's nothing in the ISA that /requires/ it to be implemented in the texture unit, more likely that's already the biggest read bandwidth connection to the memory bus so may as well piggyback off it). I honestly wouldn't be surprised if the nvidia units were implemented in a similar place - as it needs to be heavily integrated to the shader units, while also having a direct fast path to memory reads.

One big difference is that nvidia's unit can do a whole tree traversal with no shader interaction, while the AMD one just does a single node test and expansion then needs the shader to queue the next level. This means AMD's implementation is great for hardware simplicity, and if the there's always a shader scheduled that is doing a good mix of RT and non-RT instructions it's not really much slower.

But that doesn't really happen in the real world - the BVH lookups are normally all concentrated to an RT pass and not spread over all shaders over the frame. And that batch tends to not have enough other work to be doing to fill the pipeline while waiting for the BVH lookups. If you're just waiting on a tight loop of BVH lookups, the pass back to the shader to just submit the next BVH lookup is a break in the pipelining or prefetching you might otherwise be able to do.

But it might also be more flexible - anything that that looks a bit like a BVH might be able to do fun things with the BVH lookup/triangle-ray intersection instructions, not just raytracing, but there simply doesn't seem to be a glut of use cases for that as-is. And then unused flexibility is just inefficiency, after all.

I doubt they were surprised at all. Isn't RDNA3 very similar to RDNA2? They could have fixed it there, and they decided on minor improvements instead.

Wasn't RDNA2 designed with Sony and Microsoft having an input on its features? I'm sure Sony and MS knew what was coming from Nvidia years in advance. I think Mark Cerny said developers even wanted a 16 core originally, and they were talked out of it, because they had die area restrictions. RT hardware area on those consoles probably would have equaled an extra 8 CPU cores in area if they wanted Nvidia-like RT. All just seems like cost optimization to me.