dotjzzz

Technically yes

Techunically IMPOSSIBLE. Not on any existing APU chips or Zen4c chiplet. There's no TSV contacts to connect the cache.

It'll require a complete redesign of the chip. But it's possible if AMD did that.

but AMD had used monolithic dies for their APUs

Irrelevant.

add cache on top of a bigger piece of silicon than a CPU chiplet would need a redesign at least

No. Size is completely irrelevant. Redesign is needed indeed, but it's the APU that needed redesign, not the cache.

and it would jack up prices quite significantly

No. The filler silicon ALSO USED ON CURRENT X3D costs a few cents at most. Even 200mm² costs pennies.

reducing prices

Funny how increasing supply chain cost will reduce price.

For comparison, AMD’s 7950X gets 84.06 ns using 4 KB pages over a 1 GB array. AMD’s Phoenix suffers from higher latency and hits 126.7 ns with the same 1 GB test size.

It's a bit annoying when he wrote "for comparison" but these are of UNKOWN quality. 84.06ns on what memory configuration? Suffers from 126.7ns on what configuration?

Previously graph shows bandwidth of less than 100GB/s, and it looks like 85-90GB/s. It could be LPDDR5-5500 or DDR5-5600 of various timings. Again no mention if these are even on the same system. 126ns sounds like JEDEC DDR5-5600B. So if the desktop is using something like DDR5-6000 CL36 then that latency really has nothing to do with Phoenix.