Hardware

TSMC's upcoming N2 fabrication process is set to offer several improvements compared to the current N3E manufacturing technology. It is projected to deliver performance gains of 10% to 15% (at the same power and complexity), while also cutting power consumption by 25% to 30% (at the same clocks and complexity). Furthermore, the shift to the N2 node will likely enhance transistor density by about 15% on average. In general, transition from N3E to N2 brings similar improvements as transition to N3B from N5.

I don’t know how much longer we can keep going before physics ends advancement. Guess this is why quantum computing has been in development for most of my life, but I’m not sure how far off that is given that, as I said, we’ve been pursuing it most of my life and I don’t have a quantum computer. Maybe we’ll discover other breakthrough ways of doing math (I mean, undoubtedly). I’m just not educated enough to fathom the reality of what is possible in these areas.

Worth pointing out that wafers alone are a relatively small part of the cost of semi conductors.

A 300 mm wafer has about 70,000 mm^2 of area. A Zen 5 chiplet (8 core CCD) seems to be about 70 mm^2. Assuming a 60% yield, that's 600 Zen 5 chiplets.

An 8-core 9700X goes for $350.

So that works out to $210 K revenue for a $30 K wafer. Although I suspect TSMC may also get additional revenue for value add features and services.

That being said, wafer costs are increasing at a very high rate that only seems to be accelerating.

Good position for TSMC to be in, essentially getting a 15% cut for the price of any leading edge semiconductor.

It doesn't go straight from wafer to retail. The margins will likely be much thinner. There's also the cost of chip packaging, plus manufacturing a board you can plug into your computer or server.

Besides, every time a new process is introduced, the yields fall. Some of it may be salvagable so they go ahead and sell the parts at a lower price. That's how we get M3 Max, Pro, and regular flavor.