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Lunar Lake Leaked. Ultra-low power only, TSMC N3B. Memory on package (alien.top)

submitted 10 months ago by [email protected] to c/[email protected]

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[–] [email protected] 1 points 10 months ago (5 children)

Isn't this an obvious fake by someone who doesn't even know what MTL is set up like?

Eg: they have an 8MB L4 cache on the CPU die for LNL when MTL has a 128MB cache on SOC die.

And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.

And why use N3 when Intel will have Backside power with their 3nm node?

[–] [email protected] 1 points 10 months ago (2 children)

when MTL has a 128MB cache on SOC die.

It doesn't tho

And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.

Idk, it looks very similar to this

And why use N3 when Intel will have Backside power with their 3nm node?

Bcuz they are lame lol.

Intel talked about using TSMC N3 nodes in their products before. It won't be too surprising to see it in client CPU tiles as well.

[–] [email protected] 1 points 10 months ago

https://www.tomshardware.com/news/intel-patent-reveals-meteor-lake-adamantine-l4-cache

https://www.phoronix.com/news/Linux-Patch-Intel-MTL-L4-Cache

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