this post was submitted on 12 Nov 2023
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Technically yes, but AMD had used monolithic dies for their APUs for years and trying to add cache on top of a bigger piece of silicon than a CPU chiplet would need a redesign at least and it would jack up prices quite significantly and most likely we would only see a single SKU with it.
I'd guess a better alternative would be a chiplet based APU that's similar to Navi 32/31 design (GPU die surrounded by cache chiplets). It would be quite malleable, you could add a Zen X/Zen XC chiplet (or a hybrid of both that you can add 3D V-Cache on top if you wish), a GPU chiplet and a cache chiplet to keep more data to the GPU so it's less reliant on RAM bandwidth.
Probably AMD may do that in the near future with a RDNA 4/5 APU, the main problem is power consumption (Transferring data between chiplets consumes more power than a monolithic chip with all of its components in a single die) and that would be a significant downside for mobile devices, that's why they haven't made a chiplet based APU yet and it's easier to just recycle/resell any laptop APU as a desktop one.
Also there is HBM memory route. Shame that this technology isn't cheaper.
Yes, for the looks of it Intel's alternative to compete with 3D V-Cache is something akin to HBM but more efficient, I bet Intel would use it for their integrated graphics.
It is quite sad that HBM hasn't decreased in price significantly for it to be embedded in consumer APUs, even 2/4 GB wouldn't be that bad if HBCC (Uses system RAM as VRAM and HBM is used to cache data) could be used.
Techunically IMPOSSIBLE. Not on any existing APU chips or Zen4c chiplet. There's no TSV contacts to connect the cache.
It'll require a complete redesign of the chip. But it's possible if AMD did that.
Irrelevant.
No. Size is completely irrelevant. Redesign is needed indeed, but it's the APU that needed redesign, not the cache.
No. The filler silicon ALSO USED ON CURRENT X3D costs a few cents at most. Even 200mm² costs pennies.