My two best guesses for why TSMC N3B is used for the compute tile:
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The Compute Tile has the x86 Cores, NPU, and iGPU. Because of this, 20A couldn't be used. It could've been either Intel 3, N3B, or wait for 18A. N3B was likely the best choice
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ARL and LNL were developed in Tandem, one using internal foundries, the other external, as a post-10nm risk mitigation. Development for these CPUs likely began somewhere around 2020.