Because van gogh ain't designed for valve's gaming device. It contained blocks that supported computer vision. Microsoft and sony also customized their console socs by removing minor features they didn't need and decreased area by a lil more
this post was submitted on 28 Nov 2023
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I understand, but I wasn't aware of any computer-vision accelerating block in there.
Is there really any? Might be used for a future Steam Deck-based VR headset as it's rumored?
No. It was there because Microsoft asked AMD to add them, before canceling the Van Gogh SoC order.
Van Gogh has (suppsedly) 2.4 bn transistors while Series S has 8 bn.
Completely false. 2.4b transistors would mean it's less than 1/3 as dense on the same node while being lower performant (so HP cells are not a factor). Why on earth would you even use 7nm when 20nm (and even 28nm) can reach that density easily.
Use you brain. Just because TPU listed wrong data, doesn't mean you have to parrot it.
It has 40% the CU, 50% the CPU, 80% memory bus, nearly 100% front end (geometry, ACE etc), 100% display, video, I/O etc.
At bare minimum you are looking at 70% transistor count.
Bingo. The Steam Deck OLED's SoC seems to have cut out the Cadence DSPs, which we can see with the significantly smaller SoC (especially when combined with the new process node).
Pretty sure VGH also has more PCIe lanes on die as well, alongside full size Zen 2 cores (all console variants have a cut FPU).
So does this mean the steam deck SoC has particularly good performance in machine vision applications? This is actually relevant to my work lol
Interesting question. According to techpowerup Van Gogh has a transistor density of 14.7M / mm². Series S chip is at 40.6M / mm² though.
That is a huge difference for the same? process node. And TSMC's low power (high density) cells are actually smaller.
I think we'd need a die shot to see what is going on there.
It's the memory controller and cache subsystem. Series S talks directly to gddr6 and doesn't need nearly as much die space as all the L3 and big DDR5 memory controllers as the Ryzen APU in the steam deck.
4 more cores would take about 20 mm^(2) and 12 more CUs would take 28 mm^(2). So that would reach 210 mm^(2) (ignoring ROPs and the like, which might take some more space). However, space is cut in some other places. For example the Series S doesn't have AV1 decoding while the Steam Deck does have it. Also, as mentioned, memory controllers will have a different size.
Well for starters the memory controllers are smaller on the series s.
Its also 8 cores vs 4 cores.
The Series S also packs 24 CU. With 20 enabled for gaming. The steam deck has 8 CU
For reference the series x has 52 out of 56 enabled. the Ps5 has 36 out of 40 enabled.
Memory controllers, PCIe lanes, different video encoding and decoding blocks can affect size and most importantly, the Series S has an external south bridge / chipset, which I'm sure saves some die space on the main SoC.
the power constraints would not make it possible
This is pretty much your answer right there. The Series S is a high throughput design, packed with shaders and CPU cores with relatively little cache per core but high bandwidth high power GDDR plus optimized software. Van Gogh is a low power design where the shader count is pretty much limited by the power envelope. A large part of the chip isn't even shaders or CPU cors but other fixed function special purpose stuff. AMD could probably double Van Gogh's throuput with +10% die space but that's pointless because the power budget isn't there.