this post was submitted on 22 Nov 2023
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This is just a nitpicking question. Do Intel chips still have some space/transistors dedicated to SSE3? If they do, why can't they implement SSE3 by other, more powerful instrutions (like AVX) to save die space?

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[–] [email protected] 1 points 10 months ago (2 children)

The way x86 instructions are variable length and not self-synchronizing means that you can see up to 15% of your core's power budget go to decode if you aren't running in the small cache of decoded instructions, at least a few generations ago when last I heard. That isn't huge but it does mean that x86 architects have to put thought into how wide to make it, they can't just size it to make sure it's never a bottleneck like ARM designers can.

[–] [email protected] 1 points 10 months ago

Mate, the 90s were a few decades back. ;-)

x86 decoding hasn't been a limiter since then.